1. Field of the Invention
The present invention generally relates to virtual address translation mechanism for data processing systems and, more particularly, to an access look-aside facility which provides a significant performance benefit for storage accesses. The environment of the invention is a data processing system in which a program or programs being executed on the data processing system have concurrent access to multiple virtual address spaces. In such a system, access registers corresponding to general purpose registers contain tokens, referred to as Access List Entry Tokens or ALETs, are used to specify an access list entry for obtaining a segment table designation in a translation process. The use of ALETs allows system control of address spaces to be isolated from program control access registers. The invention is a specific improvement to the systems disclosed in U.S. Pat. No. 4,355,355 to Butwel et al. and U.S. Pat. No. 4,979,098 to Baum et al.
2. Description of the Prior Art
Virtual storage organization and management for data processing systems are described, for example, by Harvey M. Deitel in An Introduction to Operating Systems, Addison-Wesley (1984), by Harold Lorin and Harvey M. Deitel in Operating Systems, Addison-Wesley (1981), and by Harold S. Stone in High-Performance Computer Architecture, Addison-Wesley (1987). In a virtual storage system, paging is a relocation and address-to-physical-location binding mechanism providing the user of the system with what appear to be considerably larger memory spaces than are really available. The key feature of the virtual storage concept is disassociating the addresses referenced in a running process from the addresses available in main storage. The addresses referenced by the running process are called virtual addresses, while the addresses available in main storage are called read addresses. The virtual addresses must be mapped into real addresses as the process executes, and that is the function of the dynamic address translation (DAT) mechanism. One such mechanism employs a directory look-aside table (DLAT), sometimes referred to as a translation look-aside buffer (TLB), which stores recent virtual address translation. For virtual addresses stored in the DLAT, the translation process requires only a single or, at most, a couple of machine cycles. For addresses not stored in the DLAT, the DAT process may take from fifteen to sixty cycles.
Translations from the virtual address to the real address must be made to find where the addressed instruction or data is in main storage. This is typically done on a page basis. In fact, the translations stored in the DLAT are actually only page translations, and the last bits of an address are the location in that page, so only the page address must be translated.
U.S. Pat. No. 4,355,355 to Butwell et al. discloses an address generating mechanism for multiple virtual spaces wherein in access registers (ARs) are associated with the general purpose registers (GPRs) in a data processor. The ARs are each loaded with a unique Segment Table Descriptor (STD) which comprises a segment table address in main storage and a segment table length field. In the embodiment disclosed, there are fifteen ARs associated with fifteen GPRs to define a subset of up to fifteen data address spaces. The Butwell et al. invention requires that the STD be in the AR, and therefore, as a practical matter, the number of STDs available to the DATA hardware is limited (e.g., fifteen in the case of the embodiment disclosed).
U.S. Pat. No. 4,979,098 to Baum et al. disclosed an architecture embodying the use of multiple address spaces. The Baum et al. invention is an improvement of the invention described in the Butwell et al. patent. More particularly, Baum et al. describe an Access Register Translation (ART) process wherein the results of the ART process are stored in an ART Look-aside Buffer (ALB) for later use. Baum et al. describe Control Registers CR2, CR5 and CR8 (the "DSI CRs" of the Butwell et al. patent) and how they affect the ALB.